1. Field of the Invention
The present invention relates to synchronized counter circuits which operate in synchronization with clocks, and more specifically to counter circuits having load functions with which count initiation values are able to be set.
2. Background Art
Methods for arranging counter circuits wherein two or more counter circuits are "multi-digit connected" are known to be useful when the number of digits in the values being counted are large. "Multi-digit connection" refers to a connection method wherein counter circuits are connected in multiple stages in such a way that a carry output from a lower-digit counter circuit is connected to a count enablement input terminal of a higher-digit counter circuit.
Additionally, in order to allow counting of the count values to commence at an arbitrary value, a conventional method is to introduce a count initiation value into the counter circuit by means of a load signal and to begin the counting operation upon release of the load signal.
Such a conventional counter circuit having a load function for counting values from an arbitrary value is illustrated in FIG. 5 in the form of a block diagram. In FIG. 5, reference numerals 1-1.about.1-N indicate counter circuits, reference numeral 4 indicates a load signal input terminal, reference numeral 5 indicates a load value input terminal, reference numeral 6 indicates a count enablement input terminal and reference numeral 7 indicates a count value output terminal.
Next, the operation of the counter circuits 1-1.about.1-N of FIG. 5 will be explained with reference to FIG. 3. Each of the counter circuits 1-1.about.1-N operates in synchronization with a clock input, and when the load signal input terminal 4 is at LOW level, the inputted value is set at the load value input terminal 5 with the rising of the clock pulse. Additionally, when the load signal input terminal 4 is at HIGH level and the EP terminal and ET terminal are also at HIGH level, each of the counter circuits 1 goes into a counting state and commences a counting operation upon reception of the input clock pulse at the clock input CK.
The carry output CO of each counter circuit 1 releases a HIGH level output when the count value is in a state such that the next clock input would result in a promotion to the next digit, that is, when a full count value is being output. When either the EP terminal or the ET terminal is at LOW level, the counter circuit goes into a count prevention state, and maintains such a state without performing any counting operations even if a clock signal is input. In particular, when the ET terminal is at LOW level, the carry output always outputs a LOW level signal.
As shown in FIG. 5, the counter circuit 1-1 counts the lowest digit in the count value output from the count value output terminal 7. Then, the carry output of the counter circuit 1-1 is connected to the EP terminals of the higher digit counter circuits 1-2.about.1-N. Additionally, the count enablement input terminal 6 is connected to the EP terminal and ET terminal of the first counter circuit 1-1, and the ET terminal of counter circuit 1-2 is always held at HIGH level. Furthermore, to the ET terminals of the counter circuits 1-3.about.1-N corresponding to the each of the higher digits, the carry output of the next highest digit is input.
During normal operation of the counter, a counting operation is performed when the counter circuit 1-1 goes into a full count state and releases a carry signal while a carry signal is output from the counter circuit of the next highest digit for each counter circuit 1-2.about.1-N.
An operational example of this circuit will be explained with reference to the time chart given in FIG. 6. The time chart of FIG. 6 shows an example wherein the counter 1-1.about.1-N of each digit counts up the digits "0".about."F", in hexadecimal notation, with a 4-bit upcounter.
First, the counter circuit with load function is put into a count-ready state when the count enablement signal input terminal 6 is put at HIGH level. The load value "0FFE" is set at the load value input terminal 5, and when the load signal input terminal 4 is at LOW level, a load value is loaded into each counter circuit 1-1.about.1-N with the reception of a clock pulse. At this time, a promotion to the next digit occurs in the counter circuit 1-2 with the next count, and a carry output CO is output because the ET terminal is at HIGH level.
Although a promotion also occurs in counter circuit 1-3 with the next count, a carry output CO is not output until a HIGH level signal is input to the ET terminal of this counter circuit. That is, defining td1 to be the duration of time from clock pulse to the carry output CO and td2 to be the duration of time from the signal input at the ET terminal to the carry output CO, then the amount of time elapsed between the input of the clock signal to the carry output for the counter circuit 1-3 would be td1+td2.
Therefore, if a counter circuit having load function is composed of N counter circuits, when a value such that the next count would result in a promotion is read into counter circuits 1-2.about.1-(N-1), the time elapsed from the clock pulse until the input of the carry output CO of counter circuit 1-(N-1) to the ET terminal of the counter circuit 1-N would be td1+td2*(N-3).
After the input at the ET terminal of each counter circuit 1-1.about.1-N has been defined, the counter circuit having load function counts up 1 each time the load signal input terminal 4 becomes HIGH and a clock pulse is input. For this reason, in the case in which the load value is "0FFF", if this load value is loaded into the counter circuits 1-1.about.1-N corresponding to each digit, there is the possibility that a promotion to the next digit will occur in counter circuit 1-4 with the clock signal released right after a carry output CO has been output from the lowest digit counter circuit 1-1. In order for the counter circuits 1-1.about.1-N corresponding to each digit to operate correctly after the load values have been loaded, the input to the ET terminal for each counter circuit 1-1.about.1-N must be defined before the next clock input.
If the period of the input clock is very long in comparison to the signal definition time of the ET terminal of each of the counter circuits 1-1.about.1-N, or if the counter circuit 1-1 does not contain a load value such that the next count would result in a promotion to the next digit, in other words, if there is no full count value, the delay time of the ET terminal input does not present a problem. However, when the input clock period is short and a full count has been set at the load value input terminal 5 of the counter circuits 1-1.about.1-N, then the counter circuit 1-N cannot perform a proper count because, due to the delay time, the next clock pulse is input before the ET terminal input of counter circuit 1-N is defined.
Consequently, there have been problems whereby conventional counter circuits having load functions could not output the correct counter values, resulting in faulty operations. As the number of counter circuits 1-1.about.1-N composing the counter circuit having load function increases, the delay time td2 elapsed between the signal input to the ET terminal of the counter circuit until the release of the carry output CO accumulates. When designing a conventional counter circuit under consideration of this delay time so that faulty operations do not occur, there is a problem in that the input clock period must be chosen to be able to handle the time elapsed until the signal definition at the ET terminal of the N-th counter circuit, slowing the operation speed of the entire circuit.